Integrated logic circuit

ABSTRACT

An integrated circuit having a combinational circuit and two field effect transistors formed on a common semiconductor substrate, and in which the two field effect transistors are made conductive alternately by two clock pulses without a direct current source.

United States Patent Shlaeyuld Ochi;

Tetsuo Ando, both of Tokyo, Japan 868,800

Oct. 23, 1969 Nov. 23, 1971 Sony Corporation Tokyo, Japan Oct. 23, 1968 Japan July 31, 1969, Japan, No. 44/60884 Inventors Appl. No. Filed Patented Assignee Priorities INTEGRATED LOGIC CIRCUIT 6 Claims, 39 Drawing Figs.

US. Cl 307/205,

307/22 1 307/238, 307/246, 307/25 1, 307/279 H03lt 17/60 307/205,

Int. C Field of Search [56] References Cited UNITED STATES PATENTS 3,524,077 8/ I970 Kaufman 307/246 OTHER REFERENCES Boysel et al., Multiphase Clocking Achieves 100- N Sec. MOS Memory, Electronic Design News, June 10, 1968, pp. 50- 52, 54, & 55.

Primary ExaminerStanley T. Krawczewicz Attorneys-Lewis H. Eslinger, Alvin Sinderbrand and Curtis,

Morris & Saflord ABSTRACT: An integrated circuit having a combinational circuit and two field effect transistors formed on a common semiconductor substrate, and in which the two field effect transistors are made conductive alternately by two clock pulses without a direct current source.

PATENTEDunv 23 197i sum u DF 5 IN V/ 1'/ (1R5 SHIGEYUKI OC HI TETSUO ANDO PATENTEDHBV 23 an 3,522,79

sum 5 [IF 5 INVI'LN'IURJ SHIGEYU Kl OCHI TETSUO ANDO INTEGRATED LOGIC CIRCUIT This invention relates generally to integrated logic circuits, and more particularly to ratioless'type integrated logic circuits using two-phase clock pulses.

Metal insulator semiconductor (MIS) field effect transistors or metal oxide semiconductor (MOS) transistors have been recently employed in digital logic circuits for the following reasons.

Large-scale integrated circuits using the MOS transistors require relatively few diffusion processes in manufacture and hence are relatively easily fabricated with a low percentage of rejects due to manufacturing defects. Further, such integrated circuits have a relatively low power consumption. However, a logic circuit employing a conventional ratio-type MOS transistor requires many large-sized MIS transistors as loads and this imposes a limitation on the number of transistors that can be provided on a semiconductor substrate of a given size.

Although a conventional ratio-less type logic circuit permits the use of small MIS transistors so that relatively large numbers of the transistors can be provided on a substrate of a given size, this circuit also necessitates power source conductors for supplying power to the MIS transistors, grounding conductors and conductors for a threeor four-phase clock pulse, in addition to conductors connected with the input and output terminals. The electric fields of these conductors exert an influence upon the substrate, so that the transistors cannot be disposed as close to one another as would otherwise be expected and the overall power consumption cannot be reduced to the full extent made possible by the small MIS transistors.

Accordingly, it is an object of this invention to provide integrated circuits that are free of the above-mentioned disadvantages of previously proposed circuits using MOS or MIS transistors.

A specific object of the invention is to provide compact integrated logic circuits that do not require a DC power source.

Another object is to provide integrated logic circuits in which the semiconductor substrate common to all of the transistors functions as a grounding conductor.

A further object is to provide digital logic circuits employing relatively small numbers of transistors.

A still further object is to provide ratio-less type integrated circuits which are operated by the supplying of clock pulses thereto, and which do not require a DC power source.

Such ratio-less type integrated circuits according to the invention have the following advantages:

1. The clock pulse may be two-phase so that the wiring or conductors required for the integrated circuit are simplified.

2. Since the MIS transistors employed may be of the same miniaturized size, their density on a common substrate may be high and their switching speed is high.

3. Since the signal level is determined independently of the transconductance g of the MIS transistors, dispersion caused in the manufacture of the MIS transistors does not matter and this facilitates the fabrication of the integrated circuit. Further, the resulting integrated logic circuit is not adversely affected by noise.

4. A current flows in the circuit only when a clock pulse is supplied and it is sufiicient only to charge the stray capacity of the MIS transistor circuits, so that power consumption is small.

5. Neither a DC power source nor interconnections for power source supply are required.

6. A grounding connection need not be provided on the upper surface of the integrated circuit and instead the substrate is utilized as a conductor to ground. Accordingly, an insulator for example of silicon dioxide or silicon nitride, can be formed thin on the integrated circuit, and hence production of the integrated circuit is facilitated.

7. Since the current of the clock pulse flows only when the stray capacity is charged, a clock pulse generator that is simple in construction may be employed as the source of the clock pulses.

The above and other objects, features and advantages of the invention, sill be apparent in the following detailed description of illustrative embodiments to be read in connection with the accompanying drawings, in which:

FIGS. 1, 3 and 5 are circuit diagrams of integrated logic circuits according to several embodiments of the invention;

FIGS. 2, 4 and 6 are waveform diagrams to which reference will be made in explaining the operation of the embodiments of FIGS. 1, 3 and 5, respectively; and

FIGS. 7A, 7B and 7C are circuit diagrams of several combinational circuits that can be employed in logic circuits embodying this invention.

Generally, in accordance with this invention, a circuit comprises two MIS transistors and having no power source terminal and a combinational circuit consisting of an AND gate circuit, an OR gate circuit, a bridge circuit or a combination thereof, also having no power source terminal and such components are formed as one unit on the same semiconductor substrate to provide an integrated logic circuit.

In FIG. 1 there is illustrated a delay multivibrator circuit having the foregoing general arrangement and in which the MIS transistors are N-type enhancement insulated gate field effect transistors. If the polarity of a voltage used is reversed, P-type insulated gate field effect transistors can be employed.

In FIG. 1, reference character A indicates a combinational circuit which is made up of a single MIS transistor M, having neither a power source terminal nor an input terminal for clock pulse supply. The gate of MIS transistor M, is connected to an input terminal T, and the source of MIS transistor M, is connected to the gate and source of a MIS transistor M,, with the gate and source of MIS transistor M being also connected to a first clock pulse input terminal t,. The drain of MIS transistor M, is connected to a junction X, which is also connected to the drain of MIS transistor M and the source of a MIS transistor M The gate of MIS transistor M,, is connected to a second clock pulse input terminal 1 Thus, a circuit unit according to this invention is provided the output of which is derived from the drain of MIS transistor M Further, in the embodiment of FIG. I, the drain of MIS transistor M,, is connected through a junction X to the gate of a MIS transistor M, of a combinational circuit A which has neither a power source terminal nor a clock pulse input terminal. The source of the MIS transistor M,, is connected to the second clock pulse input terminal l and to the gate and source of a MIS transistor M,,. Further, the drain of MIS transistor M is connected to a junction X, which is also connected to the drain of MIS transistor M and the source of a MIS transistor M,,. An output terminal T is connected to the drain of M IS transistor M,, and the gate of MIS transistor M is connected to the first clock pulse input terminal t,. In this case, the MIS transistors M, to M are formed on a common semiconductor substrate and means (not shown) connect the substrate to ground.

A clock pulse CP,, such as is shown in FIG. 2A, and another clock pulse CP such as is depicted in FIG. 2B, which has the same period as that of clock pulse CP, but a predetermined "phase difierence therefrom, are respectively applied between the terminals 1,, t and the substrate ground.

In the following description of the operation of the circuit shown in FIG. 1, it will be assumed that the input terminal T, is supplied with an input pulse 5,, such as is depicted in FIG. 2C, which rises and falls in correspondence with the occurrence of pulses of the clock pulse CP,. Further, in the following description a positive logic is used and a higher level of two values will be referred to as a level I and a lower level as a level 0."

With the input pulse S, applied by way of terminal T, to the gate of transistor M,, the transistor M, is in the on state during each period when the input pulse S, is at the level I and is in the off state during each period of the level 0. Further, upon application of a clock pulse CP, to the gate of transistor M transistor M is turned on in the duration of the pulse CP, and, since the pulse CP, is also applied to the source of transistor M the stray capacity, formed between the junction X, on the drain side of transistor M and the substrate and the wiring for the clock pulse are charged, whereby there is produced at the junction X, an output of the level 1" for the duration of the pulse CP,. When the pulse CP, decays, transistor M, is changed to its off state and if the transistor M, is then in the on state, the charge stored at the junction X, which is the output of the level l is discharged through transistor M, to provide an output of the level at junction X,. If, at the time of the decay of pulse CP,, transistor M, is in the of? state, the output of the level 1" at the junction X, is held unchanged. Consequently, an output 8,, such as is depicted in FIG. 2D, is produced at junction X,in response to the input pulse S, at terminal T,.

With application of the clock pulse CF, to the gate of transistor M,, transistor M, is turned on for the duration of the pulse CP, during which the level at the junction X, is 0." Accordingly, if transistor M, is in the on state when the level at the junction X, of the drain side of the transistor M, is l," the charge at junction X, is discharged through transistors M, and M, to lower the level at junction X, down to 0" and hold it unchanged. If the level at junction X, is I," and consequently the transistor M, is held in the off state, the stray capacity at junction X, is charged by the charge at junction X, up to the level 1" and, when the clock pulse CP, has decayed to the level 0" to turn off transistor M,, the state at junction X, is memorized, so that there is produced at junction X, an output pulse 8,, such as is shown in FIG. 2B in response to the output pulse S, at junction X,. It will be seen that the original S, is the inverse of the input original 8,, and is delayed by one-half period behind the input signal S,. The foregoing represents the fundamental operation of a logic circuit unit according to this invention.

Further, in the circuit of FIG. I, the output pulse S, is produced at the junction X, and is applied to the gate of transistor M, to hold it in the on state in the period of the level 1" of the pulse S, and hold it in the off state in the period of the level 0" of the pulse. While the clock pulse CP, is applied to the gate of the transistor M, to turn it on during the duration of the pulse CP,, the pulse CP, is also applied to the source of transistor M, to produce an output of the level 1" at junction X, at the drain side of transistor M, during dura tion of the pulse CP,. After the duration of the pulse CP,, the transistor M, is turned off and, if transistor M, is in the on state, the charge at junction X,, which is an output of the level I, is discharged through transistor M, to produce an output of the level 0 at junction X,,. If transistor M, is in the off state, the output of the level l at junction X, is held unchanged. Consequently, there is derived at junction X, an output pulse S, such as is depicted in FIG. 2F in response to the output pulse S, at junction X,.

Under such conditions, the pulse CP, is applied to the gate of transistor M, to turn it on for the duration of the pulse CP, and, if the level of the output pulse S, at junction X, is 1" while transistor M, is in the on state, an output of the level I is produced at the drain side of transistor M, and consequently at the output terminal T,. In the event that the level of the output pulse at junction X, is 0," an output of the level 0 is derived at the output terminal T,. Thus, there is produced at output terminal T, an output pulse 8,, such as is shown in FIG. 20 in response to the output pulse S, at junction X,,.

Accordingly, it will be apparent that application of the input pulse S, FIG. 2C to the input terminal T, results in the output pulse S, FIG. 26 being produced at the output terminal T,. A comparison of the input pulse S, and the output pulse S, shows that the output pulse S, is delayed behind the input pulse 8, by one period of the clock pulse, that is, by one bit time. Thus the circuit described above with reference to FIG. 1 functions as a delay multivibrator.

It will be apparent from the foregoing that the MIS transistor M, to M, operate with the clock pulse as a power source and that the transistors are not otherwise supplied with power from any external source. Thus, there is no continuous DC current flow in the transistors M, to M, and, in addition, the current for the clock pulse supply is a mere charging current for the small stray capacity. Therefore, the overall consumption of the circuit is extremely low.

Further, since DC current is not supplied to the transistors M, to M, at all times, the usual power source of such DC current and power source the wiring or conductors therefor are unnecessary, which makes possible simplification of the overall construction, especially when the transistors M, to M, are formed on a common semiconductor substrate as previously described. Further, in circuits according to the invention the semiconductor substrate is grounded, so that individual conductors for grounding the semiconductor substrate for the respective transistors are unnecessary and this further simplities the overall circuit construction.

Since transistors M, and M, are in the 011' state at the time when the levels of the outputs at junction X, and terminal T, are 0, the mutual conductance of transistors M, and M, need not to be so low as that required in the case where transistors M, and M, serve as loads in order to produce a step valve from the output level 0" to the output level 1" which is sufliciently high to cause the output level to be 0" at junction X, and terminal T,. Accordingly, transistors M, and M, need not be larger in size than transistors M, and M,, as distinguished from existing ratio-type logic circuits. Therefore, this invention makes possible the production of the integrated logic circuit on a semiconductor substrate of small area. On the other hand, if transistors M, and M, were made to be in the on state and a current could be applied to junctions X, and X, at the time when the output levels at junction X, and terminal T, are 0," the output level "0" could not be made to have a sufficiently great difference from the output level 1" unless the mutual conductance of transistors M, and M, was sufficiently decreased or that of transistors M, and M, was very substantially increased so as to provide the 0 output level at power junction X, and the terminal T,. Further, since transistors M,

' as is shown in FIG. 2G.'

and M, need not have a low mutual conductance, it is possible to substantially shorten the rising time of pulses S, and S, when transistors M, and M, are in the on state, thereby to raise the clock pulse frequency and allow high-speed operation of the integrated logic circuit. In addition, even if the pulse width of the clock pulse is widened, the current flow is only enough to charge a small stray capacity of the circuit and memorize it. Therefore, it is not necessary to use a clock pulse of small pulse width to maintain a low power consumption, as widening of the pulse width will not appreciably increase the power consumption.

In the foregoing, the period of the clock pulse CP, has been issued to be equal to that of the clock pulse CP,. However, even if a clock pulse CP,', such as is depicted in FIG. 2B, is employed which is synchronized with the pulse CP, of FIG. 2B, but is produced at intervals of a multiple of the period of the pulse CP,, the output pulses 8,, S, and S, at junctions X,, X, and X,, respectively, become as shown in FIGS. 2D, 2E and 2F in response to the input pulse S, depicted in FIG. 2C, thus deriving at the output terminal T, an output pulse S, such Turning now to FIG. 3, it will be seen that the present invention is there shown applied to another delay multivibrator circuit, in which elements corresponding to those in FIG. 1 are identified by the same reference numerals. In the circuit of FIG. 3 the drain of a MIS transistor M, is connected to the gate of MIS transistor M,, the gate of transistor M, is connected to the source of transistor M, and input terminal T, is connected to the source of transistor M,. In this case, MIS transistor M, again constitutes a combinational circuit A having neither a power source terminal nor an input terminal for clock pulse supply. The drains of MIS transistors M, and M, are interconnected and connected to the source of MIS transistor M,,. The source of transistor M, and the source and gate of transistor M, are connected together and connected to the first clock pulse input tenninal 1,. The gate of transistor M,, the source of MIS transistor M, and the source and gate of MIS transistor M, are connected to the second clock pulse input terminal t,. Further, the drain of transistor M, is con- "1." As a result of this, an output pulse 5, such as is shown in FIG. 46 is produced at the terminal T, in response to the output pulse S, at junction X Thus, when the input pulse S, shown in FIG. 4C is applied to input terminal T,, the output pulse S, depicted in FIG. 46 is produced at the output terminal T and it will be seen that output pulse 5,, is similar to the input pulse 8,, but delayed with respect to the latter by one bit time. Accordingly, the cirwith an input pulse S, such as is depicted in FIG. 4C and which again rises and falls in correspondence with pulses of the clock pulse CP,.

When the clock pulse CP, is applied to the gate of transistor M, to turn it on for the duration of the pulse CP,, and if the level of the signal S, fed to input terminal T, is 0," the out- 1 put level at junction X, on the drain side of transistor M becomes 0 and, if the level of signal S, is l, the level of the output at junction X, becomes I." Thereafter, when the level of the clock pulse CP, becomes 0 to turn off the transistor M,, the state of junction X, is memorized, so that an output pulse 8,, such as is depicted in FIG. 4D is derived at junction X, in response to signal S,.

The pulse signal S, is applied to the gate of transistor M so that transistor M, is caused to be in the on state while pulse S is at the level 1" and transistor M, is held in the off state while pulse S is at the level 0. The clock pulse CP, is applied to the gate and source of transistor M to turn it on, and the charge by the current of the clock pulse CP, produces at cuit as illustrated in FIG. 3 also performs the function of a delay multivibrator circuit.

Further, it will be understood that the same operational effects as those previously described with reference to FIG. I can be obtained with the construction of FIG. 3.

The foregoing description of operation has assumed that the period of the clock pulse CP, is equal to that of the clock pulse CP,. However, even if a clock pulse CP,', such as is shown in FIG. 4A, is employed which is synchronized with the pulse CP, of FIG. 4A but produced at intervals of a multiple of the 0 period of the pulse CP,, the output pulses S S and S at the junction X, on the drain side of transistor M, an output whose level is I for the duration of the pulse CP,. When the pulse CP, decays, transistor M is turned off, in which case, if transistor M, remains in the on state, the charge at the junction X,', where the output has been at the level I," is

discharged through transistor M, to produce an output of the level 0" at junction X,. In the event that transistor M, is in the off state where pulse CP, decays, the output of the level 1" at junction X, is held unchanged. Consequently, an output pulse 8;, such as is depicted in FIG. 4E is derived at junction X in response to the signal 8,.

Further, the clock pulse CP, is applied to the gate of transistor M,, to hold it in the on state for the duration of the pulse' CP during which the output at junction X, is at the level 0." Consequently, in the event that transistor M, is in the on state when the output at junction X, on the drain side of transistor M,, is at the level l," the charge at junction X, is discharged through transistors M, and M to lower the level of the signal at junction X, to 0. On the other hand, when the level of the signal at junction X is 0, such signal remains unchanged. When the signal at junction X, is at the level 1,"

and hence transistor M, is in the 05 state, the signal at junction X, is charged up to the level 1 by the charge at junction X and the level of the clock pulse CP, is lowered to 0 to turn off transistor M,, and the state at junction X is memorized. Consequently, an output pulse 8., such as is shown in FIG. 4F is produced at junction X, in response to '7 the output pulse 8,.

The resulting output pulse S, is supplied to the gate of transistor M,, so that transistor M,, is in the on state while pulse S, is at the level l and transistor M,, is in the off state when the pulse S, is at the level 0." The clock pulse CP, is applied to the gate of transistor M,, to turn it on and hold it in the on state for the duration of the pulse CP,, and, at the same time, the pulse CP, is fed to the source of transistor M,,, by 5 which an output of the level 1 for the duration of the pulse CP, is produced at a point on the drain side of the transistor M,,, that is, at the output terminal T by the current of the clock pulse CP, flowing in transistor M,,. Upon the decay of the pulse CP transistor M,, is turned off and, if transistor M,, is

then in the on state, the charge at terminal T which has been an output of the level 1" is discharged through transistor M,, producing an output of the level 0" at terminal T If transistor M is in the off state upon the decay of pulse CP the output at output terminal T is held unchanged at the level junctions X,', X, and X respectively, are then illustrated in FIGS. 4D, 45 and 4F as a result of the input pulse S, shown in FIG. 4C, thus producing at the output terminal T an output pulse 8,, as depicted in FIG. 46.

Referring now to FIG. 5, it will be seen that the present invention is then shown applied to a set-biased multivibrator circuit, in which the MIS transistors are P-type enhancement insulated gate field effect transistors and elements similar to those of FIG. I are identified by the similar reference numerals. In the circuit of FIG. 5, a reset signal input terminal R is connected to the gate of a MIS transistor M, constituting a combinational circuit A having neither a power source terminal nor a clock pulse input terminal, and the source of transistor M, is connected to the gate and source of a MIS transistor M The gate and source of transistor M, are interconnected and the connection therebetween is connected to a first clock pulse input terminal t,. The drain of transistor M, is connected at a junction Y, with the drain of transistor M and with the source of a MIS transistor M The gate of transistor 0 M, is connected to a second clock pulse input terminal 1,. The

drain of transistor M,, is connected at a junction Y to the gate of a MIS transistor M The source of transistor M,, is connected to the drain of a MIS transistor M,,, which in turn, has its source connected to the second clock pulse input terminal t Further, the drain of the transistor M,, is connected, at a junction Y,,, with the source of a MIS transistor M and with the drain of a MIS transistor M,,. The gate and source of transistor M,, are connected to the second clock pulse input terminal A connection point between the drains of transistors M,, and M,, is connected to the drain of a MIS transistor M,,, and the source of the latter is connected to the second clock pulse input tenninal I, while the gate of transistor M,, is connected to a set signal input terminal S. The gate of transistor M,,, is connected to the first clock pulse input terminal t, and the drain of transistor M,,, is connected to the gate of a MIS transistor M,,. The drain of transistor M,,, is connected, at a junction Y with the drain of a MIS transistor M,,, and with the source of a MIS transistor M,,. The source of transistor M,,, and the gate and source of transistor M,,, are all connected to the first clock pulse input terminal t,. The gate of transistor M,,, is connected to the second clock pulse input terminal and its drain is connected to an output terminal T and to the gate of transistor M Also in this case, the MIS transistors M, to M,, and M,, to M,, are formed on a common semiconductor substrate, which is grounded. It will be seen that a circuit A constituted by transistor M,, a circuit A made up of the interconnected MIS transistors M,,, M,, and M,, are a circuit 1 constituted by the MIS transistor M,,, are combinational circuits which have neither power source terminals nor clock pulse input terminals.

A clock pulse CP,, such as is shown in FIG. 6A, is applied to the first clock pulse input terminal I, and a clock pulse CP such as is depicted in FIG. 6B, is fed to the second clock pulse input terminal t,. The embodiment of FIG. 5 has been described as employing P-type enhancement insulated gate field effect transistors as the MIS transistors. However, if the polarity of the voltage of the clock pulse used is reversed, N- type insulated gate field effect transistors can be employed.

In the following description of the operation of the circuit in FIG. 5, a negative logic is used and a higher level of two values will be referred to as a level and a lower level as a level 1. Further, it will be assumed that the reset signal input terminal R is supplied with a reset input pulse R, such as is shown in FIG. 6C and which falls in synchronization with clock pulse CP, and that the set signal input terminal S is supplied with a set input pulse 8,, such as is depicted in FIG. 6D and which falls in synchronism with clock pulse CP,.

The reset pulse R is applied to the gate of transistor M, so that transistor M, is held in the on state while the reset pulse R is at the level 1 and the transistor is in the off state while the pulse R is at the level 0."

The clock pulse CP, is fed to the gate of transistor M so that transistor M is held in the on state for the duration of the clock pulse CP, and, at the same time, the pulse CP, is applied to the source of transistor M whereby an output of the level I is produced for the duration of the pulse CP, at junction Y, on the drain side of the transistor M, by the current of the clock pulse CP, flowing through transistor M When the pulse CP, decays to turn 01? transistor M, and, at such time, transistor M, is in the on state, the charge at junction Y, where the output has been at the level 1" is discharged through transistor M, to lower the output at junction Y, down to the level 0. In the event that the transistor M, is in the off state when pulse CP, decays, the output at junction Y, remains at the level l." Consequently, a pulse R,,, such as is shown in FIG. 6E is derived at junction Y, is response to the reset pulse R at the terminal R.

The application of the second clock pulse CF, to the gate of the transistor M holds the latter in its conductive state for the duration of the pulse CP, during which the output level at junction Y remains 0. Accordingly, when the transistor M, is in the on state, the charge of the output of the level I at junction Y, on the drain side of transistor M is discharged through transistors M, and M, to lower the output level at junction Y down to "0." When the output level at junction Y is 0," it remains unchanged. When the output level at junction Y, is 1" and consequently transistor M, is in the off state, the output level at junction Y, is charged up to 1 by the charge at junction Y,and, when the clock pulse CP, is turned off to change transistor M,, to its off state, the state at junction Y, is memorized. Thus, a pulse R such as is depicted in FIG. 6F is produced at junction Y, in response to the pulse R at junction Y,.

Further, the set pulse 8,, is fed to the gate of transistor M,, so that transistor M, is held conductive when the set pulse S is at the level 1" and the transistor M, is held nonconductive when the set pulse S is at the level 0. The clock pulse CP is applied to the gate of transistor M,, so that transistor M,, is held in the on state while the clock pulse CP, is on" and, at the same time, the pulse CP is applied to the source of transistor M,,, so that an output of the level I and a duration corresponding to the pulse duration of the pulse CP,. is produced at junction Y, on the drain side of transistor M,, by the current of the pulse Cl flowing therethrough. When the clock pulse CP, decays, transistor M,, is turned off, in which case, if the transistor M, is conductive, the charge at junction Y, is discharged through transistor M,,, producing an output of the level 0" at junction Y,,. The output at junction Y, is affected by that at junction Y Thus, when the output of the level 1" is produced at junction Y, to turn on transistor M,, and the output of the level 1 is derived at the output terminal T to render transistor M,, conductive, the charge at junction Y, is discharged through transistors M,, and M,, to provide an output of the level "0 at Junction Y In the cases where either of transistors M, and M,,, or both of them are in the off state and transistor M is in the off state, the output of the level 1 at junction Y, is held unchanged. As a result of this, a pulse S such as is depicted in FIG. 6G is derived at junction Y, in response to the set pulse 8,, at the terminal S, the pulse R at junction Y and the signal at the output terminal T The first clock pulse CP, is applied to the gate of transistor M so that transistor M,,, is held conductive while the clock pulse CP, is on." In such a case, when the output level at the point Y, is 0," that is, transistor M, is in the on state or the transistors M,, and M,, are both in the on state and the output level at junction Y, on the drain side of transistor M,,, is l," the charge at junction Y, is discharged through transistors M,, and M,,, or through transistors M,, M,, and M,,, to lower the output level at junction Y, down to "0." When the output level at junction Y, is 0" it remains unchanged. In the event that the output level at junction Y, is l," the output level at junction Y, is raised up to l by the charge at junction Y, and, when the level of the clock pulse CP, becomes "0 to turn off the transistor M,,, the state at junction Y, is memorized. As a result of this, a pulse S such as is shown in FIG. 6H is produced at junction Y, in response to the pulse 8,, at junction Y The pulse S thus produced at junction Y, is applied to the gate of transistor M,,, by which the transistor M is held conductive while the pulse S remains at the level 1" and transistor M,,, is rendered nonconductive while the pulse S is at the level 0. The clock pulse CP, is applied to the gate of transistor M,, to render transistor M,, conductive for the pulse duration of the pulse CP, and, at the same time, the pulse CP, is fed to the source of transistor M,,, through which the current of the pulse CP, flows to produce at junction Y, on the drain side of transistor M,, an output of the level 1" for the pulse duration of the pulse CP,. When the pulse CP, decays, transistor M,, is turned off, in which case, if transistor M is in the on state, the charge at junction Y is discharged through transistor M,, to produce an output of the level 0 at junction Y whereas, if transistor M,,, is in the off state, the output of the level 1" at junction Y, is held unchanged. Accordingly, a pulse 8,, such as is depicted in FIG. 6I is produced at junction Y, in response to the pulse S at junction Y,.

The pulse CP, is supplied to the gate of transistor M1 so that the transistor M,, is held conductive or in. its on state for the pulse duration of the pulse CP,. While transistor M,,, is in the on state, if the level of the output pulse as junction Y, is l, the output of the level 1" is derived at the drain side of transistor M,,, and consequently at output terminal T whereas, if the level of the output at junction Y, is 0, the output of the level 0" is produced at the output terminal T Consequently, an output pulse S such as is depicted in FIG. 61 is derived at the output terminal T in response to the output pulse S at junction Y,,.

Thus, when the set signal S is applied to the set signal input terminal S earlier than reset signal R the multivibrator circuit naturally initiates its operation with the set signal S,,. However,

if the reset signal R is applied to the reset signal input terminal R earlier than the set signal 8,, by 56 bit time, the signal 8,, shown in FIG. 6.! is produced at the output terminal T,. It will also be apparent that the same operational effects as those described with reference to FIG. 1 can be obtained with the set biased multivibrator circuit illustrated in FIG. 5.

The combinational circuits A, A, A" and A', which are made up of MIS transistors without any power source terminal and without any input terminal for the clock pulse supply, may be replaced by an OR circuit consisting of a plurality of MlS transistors connected in parallel relation as shown in FIG. 7A, or by an AND circuit consisting of a plurality of M18 transistors connected in series as shown in FIG. 7B, or by a bridge circuit consisting of MlS transistors as depicted in FIG. 7C. Further, it is also possible to use combinational circuits made up of the circuits of FIGS. 7A, 7B and 7C in combination. In FIGS. 7A, 7B and 7C, reference characters I, to I, indicate signal input tenninals and t and t designate detected output terminals.

Further, it is preferred that capacitors C, C, C" and C be connected between the gates and sources of M18 transistors M M M M and M as indicated in broken lines on FIGS. 1, 3 and 5. With the provision of the capacitors, the sources sides of M18 transistors M M M M and M are capacitively excited by the clock pulse so that, when the combinational circuits A, A, A" and A' are in the off state or the signal level at the input terminal T in FIG. 3 is "1, the level 1" of the outputs on the source sides of M18 transistors M M M M and M is increased more than in the corresponding embodiments as originally described and the outputs are derived at the output sides as charging voltages at the drain sides of transistors M M M,, M and M In any of the circuits described with reference to FIGS. 1, 3, and 5, the source and drain of each MlS transistor can be exchanged without altering the previously described operational effects.

Although several logic circuits embodying this invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to these precise embodiments, and that various modifications and changes may be effected therein by one skilled in the art without departing from the scope or spirit of the invention.

What we claim is:

I. An integrated logic circuit for delaying an input signal by one bit period and having only two clock pulse receiving terminals, said integrated circuit comprising a first combinational circuit having an input tenninal for receiving an input signal and two output tenninals and consisting of at least one first field effect transistor, two additional first field effect transistors, a second combinational circuit having an input terminal and two output terminals and consisting of at least one second field effect transistor, two additional second field effect transistors, all of said transistors having a common substrate which is grounded, each of said transistors having a gate electrode, a source electrode and a drain electrode, means connecting in parallel relation the source-drain circuit of each of said first and second field effect transistors with said two output terminals of the respective combinational circuit,

means connecting the gate electrode of one of said additional first and second field efiect transistors with one of said output terminals of said first and second combinational circuits, respectively, means connecting the source-drain circuit of the other of said additional first and second field effect transistors with the other of the output terminals of said first and second combinational circuits, respectively, means connecting said source-drain circuit of said other additional first field effect transistor with said input terminal of the second combinational circuit, means for supplying a first clock pulse to the gate electrodes of said one additional first field effect transistor and said other additional second field effect transistor by way of one of said two clock pulse receiving terminals, and means for supplying a second clock pulse to the gate electrodes of said other additional first field effect transistor and said one additional second field effect transistor by way of the other of said two clock pulse-receiving terminals, said second clock pulse avoiding overlapping with said first clock pulse, whereby said input signal delayed by one bit period is obtained through the source-drain circuit of said other additional second field effect transistor.

2. An integrated logic circuit according to claim 1, in which said first and second clock pulses are timed to render said additional first field effect transistors and said additional second field effect transistors alternately conductive.

3. An integrated logic circuit according to claim 1, in which a capacitor is connected between said other output terminal of each of said combinational circuits and said gate electrode of said other additional first and second field effect transistors, respectively.

4. An integrated logic circuit according to claim I, wherein at least one of said combinational circuits is in the configuration of an AND gate circuit. I

5. An integrated logic circuit according to claim 1, wherein at least one of said combinational circuits is in the configuration of an OR gate circuit.

6. An integrated logic circuit according to claim 1, wherein at least one of said combinational circuits is in the configuration of a bridge circuit. 

1. An integrated logic circuit for delaying an input signal by one bit period and having only two clock pulse receiving terminals, said integrated circuit comprising a first combinational circuit having an input terminal for receiving an input signal and two output terminals and consisting of at least oNe first field effect transistor, two additional first field effect transistors, a second combinational circuit having an input terminal and two output terminals and consisting of at least one second field effect transistor, two additional second field effect transistors, all of said transistors having a common substrate which is grounded, each of said transistors having a gate electrode, a source electrode and a drain electrode, means connecting in parallel relation the source-drain circuit of each of said first and second field effect transistors with said two output terminals of the respective combinational circuit, means connecting the gate electrode of one of said additional first and second field effect transistors with one of said output terminals of said first and second combinational circuits, respectively, means connecting the source-drain circuit of the other of said additional first and second field effect transistors with the other of the output terminals of said first and second combinational circuits, respectively, means connecting said source-drain circuit of said other additional first field effect transistor with said input terminal of the second combinational circuit, means for supplying a first clock pulse to the gate electrodes of said one additional first field effect transistor and said other additional second field effect transistor by way of one of said two clock pulse receiving terminals, and means for supplying a second clock pulse to the gate electrodes of said other additional first field effect transistor and said one additional second field effect transistor by way of the other of said two clock pulse-receiving terminals, said second clock pulse avoiding overlapping with said first clock pulse, whereby said input signal delayed by one bit period is obtained through the source-drain circuit of said other additional second field effect transistor.
 2. An integrated logic circuit according to claim 1, in which said first and second clock pulses are timed to render said additional first field effect transistors and said additional second field effect transistors alternately conductive.
 3. An integrated logic circuit according to claim 1, in which a capacitor is connected between said other output terminal of each of said combinational circuits and said gate electrode of said other additional first and second field effect transistors, respectively.
 4. An integrated logic circuit according to claim 1, wherein at least one of said combinational circuits is in the configuration of an AND gate circuit.
 5. An integrated logic circuit according to claim 1, wherein at least one of said combinational circuits is in the configuration of an OR gate circuit.
 6. An integrated logic circuit according to claim 1, wherein at least one of said combinational circuits is in the configuration of a bridge circuit. 